Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software

Abstract

Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. The performance of DPLL is also observed for the different variable input frequencies and result is observed up to the mark. The lock range for the DPLL and lock time is was also observed as expected.