A Comprehensive Analysis of 32nm technology of Ladner Fischer Adder using CMOS Logic, PTL, and DPTL Focusing on Power

Abstract

Adders are designed as essential components in digital signal processing and VLSI technologies. Among them, parallel prefix adders offer significant speed advantages over traditional binary adders for various electronic applications. This paper explores the design of a 4-bit Ladner Fischer Adder using different technologies like CMOS, Pass Transistor Logic, and Double Pass Transistor Logic to achieve a more efficient use of low power. These implementation results demonstrate that the Ladner Fischer adder designed with CMOS, PTL, and DPTL has reduced power consumption The simulation was performed using Dsch3 and micro wind 3.1 tool.