A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells
Keywords:
128 bytes full-custom SRAM architecture; single ended SRAM architecture, SRAM architecture; single ended layout architecture, 128 bytes SRAM memoryAbstract
Static RAM architecture is an important part in the digital data processing devices like DSP’s Micro Processors and Embedded systems for general purpose or specific purpose applications. Demand of manufacturing
compact devices are increasing day by day, to make the compact devices the design of internal circuits area also
should be reduced. This will in turn reduces the overall size of the device. In this paper two 128 bytes SRAM architectures are implemented with conventional six transistors SRAM cell and single ended three transistor SRAM cell from the scratch to layout level. The designs are compared in terms of power consumption, area, and speed with 45nm technology. The implemented design area is reduced by 57.14% with 92.37% reduced power consumption and with 89.98% improved performance.
